(a) Field of the Invention
The present invention relates to a semiconductor memory device including a sense amplifier which amplifies the potential difference between bit lines of a bit line pair.
(b) Description of the Related Art
In general, a semiconductor memory device includes an array of memory cells in a memory cell area. The memory cells each are connected to a pair of bit lines or bit line pair, and read/write operation of the data in the memory cells is performed via the bit line pair. During the a cycle, a memory cell outputs the read data to the bit line pair, whereby the potential of the bit line pair is changed based on the read data, i.e., depending “0” or “1” of the read data. A sense amplifier amplifies the potential difference between the bit line pair, to fix the potential of both the bit lines to a high level and a low level.
FIG. 16 shows a block diagram of the memory cell array in a conventional semiconductor memory device. In general, the semiconductor memory device includes a plurality of memory banks each including a plurality of memory cell mats (memory mats), two of which are shown in FIG. 16. Each memory mat includes a plurality of memory cells each located at the intersection between a bit line pair and a word line WL, which extend perpendicular to each other. The word line WL is controlled by a decoder XDEC to select a row of memory cells. When a word line WL is activated, a corresponding row of memory cells are selected and connected to respective bit line pairs, whereby data stored in the memory cells are delivered to the bit line pairs. The bit line pair includes a bit line BL and a bit line /BL, which configure complementary data lines.
A sense amplifier block including a plurality of sense amplifiers (SA) is used common to two memory mats in this example of a shared type. A shared transistor pair or transfer gate pair is interposed between the bit line pair in each sense amplifier and the bit line pair in each column of the memory mat, for controlling the coupling therebetween. In FIG. 16, for simplification of the drawing, only a single shared transistor SHR0 adjacent to memory mat MAT0 is illustrated while omitting the shared transistor adjacent to memory mat MAT1. In addition, in the description to follow, only the configuration or operation of a single column of the memory device will be described, since those of the other columns are similar. During a read/write operation, one of the shared transistors corresponding to a selected memory mat is turned ON, whereby the bit line pair BL in the sense amplifier is connected to the bit line pair in the activated memory mat.
FIG. 17 shows the circuit configuration of the sense amplifier block and the vicinity thereof. The sense amplifier includes two p-channel transistors and two n-channel transistors, and performs differential amplification of the potential difference between bit line BL and bit line /BL. Shared transistors SHR0 and SHR1 control the coupling between the bit line pair in the memory mats and the bit line pair in the sense amplifier. For example, if memory mat MAT0 is selected, shared transistor SHR0 is turned ON to couple the bit line pair in memory mat MAT0 and the bit line pair in the sense amplifier. A precharge/equaling circuit 201 precharges the bit line pair to have a potential level equal to half the power source potential, i.e., a VARY/2 voltage, while equalizing the potentials of the bit lines in the bit line pair.
The sense amplifier operates on the power source supplied through a power source line PCS which supplies a high-potential source voltage, and a power source line NCS which supplies a low-potential source voltage. During an active state of the sense amplifier, transistors FSAPT and FSAET are turned ON to receive source voltages VARY and VSSSA onto power source lines PCS and NCS, respectively. The sense amplifier performs differential amplification of the potential difference between the bit line pair, to set one of the bit lines BL and /BL at a VARY level and the other of the bit lines at a VSSSA level. During an inactive state of the sense amplifier, transistors FSAPT and FSAET are turned off, and the precharge/equalizing circuit 202 supplies a VARY/2 voltage to power source lines PCS and NCS, whereby the potential of bit line pair BL and /BL is precharged at a VARY/2 level.
FIG. 18 shows a control-signal generation circuit which controls each constituent element of the semiconductor memory device. FIG. 19 is a waveform diagram showing operation of the semiconductor memory device.
Signal R1ACT is a bank selection signal, and complementary signal RF9T is a mat selection signal, wherein mat selection signals RF9T<0> and RF9T<1>are controlled so that either one of these signals is activated. In FIG. 19, the bank is selected if the bank selection signal R1ACT rises to a high level (H-level). Memory mat MAT0 can be selected by controlling mat selection signal RF9T<0> to a H-level, and mat selection signal RF9T<1> to a low level (L-level).
Signal BLEQ is a control signal for the precharge/equalizing circuit 201 which performs precharge of the bit line pair in the memory mat. If bank selection signal R1ACT assumes a H-level and mat selection signal RF9T<0> assumes a L-level, signal BLEQ0 assumes a L-level and the precharge/equalizing circuit 201 for memory mat MAT0 is inactivated. In this case, since bank selection signal R1ACT and signal BLEQ1 assume L-level and H-level, respectively, the precharge/equalizing circuit 201 for memory mat MAT1 is activated.
Signal SHR is a control signal for the shared transistors SHR0 and SHR1. If bank selection signal R1ACT assumes a H-level and mat selection signal RF9T<1> assumes a L-level, signal SHR0 assumes a H-level, and shared transistor SHR0 for memory mat MAT0 is turned ON. In this case, since both bank selection signal R1ACT and mat selection signal RF9T<0> assume a H-level, signal SHR1 assumes a L-level and shared transistor SHR1 for memory mat MAT1 is turned OFF. At this stage, the precharge/equalizing circuit 201 for memory mat MAT1 is activated to precharge the bit line pair in memory mat MAT1 to a VARY/2 level.
Signal CSEQ is a control signal for a precharge/equalizing circuit 202 which precharges the bit line pair in the sense amplifier. Signal CSEQ assumes a L-level, if the bank is selected and any of the memory mats is selected. If signal CSEQ assumes a L-level, the precharge/equalizing circuit 202 is inactivated and power source lines PCS and NCS assume a floating state. In addition, precharge of the bit line pair in the sense amplifier is terminated. Thereafter, a word line WL is activated to couple a selected memory cell to the bit line pair, whereby the potential of the bit line pair in the memory mat and bit line pair in the sense amplifier change their potentials depending on the data read from the memory cell.
Signals RSAET and RSAPT are activation signals of low-potential power source and high-potential power source, respectively, for the sense amplifier. If signal RSAET assumes a H-level under the condition that any one of the memory mats is selected, signal FSAET assumes a H-level, which allows transistor FSAET to be tuned ON, whereby a VSSSA voltage is supplied to power source line NCS. On the other hand, if signal RSAPT assumes a H-level under the condition that any one of the memory mats is selected, signal FSAPT assumes a H-level, which allows transistor FSAPT to be turned ON, whereby a VARY voltage is supplied to power source line PCS.
After the word line WL is activated to allow the stored data to be output to the bit line pair, a sense amplifier is activated. The activation of sense amplifier is performed by controlling signal RSAET to assume a H-level, thereby raising signal FSAET to a H-level to turn ON transistor FSAET. The On-state of transistor FSAET lowers the potential of the low-potential power source line NCS of the sense amplifier from the VARY/2 level to a VSSSA level. The potential of VSSSA level of source line NCS allows one of the two n-channel transistors in the sense amplifier to turn ON, thereby lowering one of the bit lines BL and /BL having a lower potential to a VSSSA level.
Subsequently, signal RSAPT is controlled to assume a H-level and allow signal FSAPT to assume a H-level, whereby transistor FSAPT turns ON. The potential of the high-potential power source line PCS of the sense amplifier rises from VARY/2 level to a VARY level due to the turn-ON of transistor FSAPT. The VARY level of power source line PCS allows one of the two p-channel transistors to turn ON, whereby the potential of one of the bit lines BL and /BL having a higher potential rises to a VARY level. These operations of the sense amplifier fix the potential of bit line pair to a VARY level and a VSSSA level.
A read command etc. to a memory cell array is executed after completion of the sensing operation by sense amplifier, and thereafter a precharge command is issued. The word line WL is inactivated to assume a L-level after the issuance of the precharge command, to allow signals RSAET and RSAPT to assume a L-level, whereby transistors FSAET and FSAPT turn OFF to stop the power supply to power source lines PCS and NCS. In addition, mat selection signal RF9T<0> and bank selection signal R1ACT are then lowered from a H-level to a L-level, to allow signal BLEQ0, signal SHR1, and signal CSEQ to rise from a L-level to a H-level. Signal BLEQ1 and signal SHR0, which are maintained at a H-level, do not change the level thereof.
Signal BLEQ0 for memory mat MAT0 assumes a H-level, to activate precharge/equalizing circuit 201 for memory mat MAT0, whereby the bit line pair in memory mat MAT0 is precharged to a VARY/2 level. In the sense amplifier, precharge/equalizing circuit 202 is activated by signal CSEQ assuming a H-level, whereby the bit line pair in the sense amplifier is precharged to a VARY/2 level. In memory mat MAT1, shared transistor SHR1 turns ON due to signal SHR1 rising to a H-level, whereby the bit line pair in memory mat MAT1 are coupled to the bit line pair in the sense amplifier. The bit line pair in each memory mat MAT and the bit line pair in the sense amplifier are precharged by the above operations to a VARY/2 level.
The time interval between the completion of sensing by the sense amplifier and the issuance of precharge command in the operation shown in FIG. 19 is referred to as active standby period. This active standby period is specified by a maximum of, for example, 70 microseconds in the specification of the memory devices. Thus, a read/write operation is performed within the active standby period after issuing the read or write command.
In recent years, semiconductor memory devices, such as DRAM devices, have experienced a significant reduction in the power source voltage (VDD) thereof from 3.3V to 2.5V, and then to 1.8V. This voltage reduction inevitably reduces the internal, lower power source voltage VARY of the memory device from 2.4V to 1.5V, and then to 1.4V. Along with the reduction of the internal power source voltage VARY, the threshold voltage of the transistors configuring the sense amplifier is also reduced from 0.6V to 0.45V and then to 0.3V for improving the sensitivity of the sense amplifier. There is a problem, however, associated with the lower threshold in the semiconductor memory device that the leakage current increases due to the lower threshold voltage, the leakage current flowing across the transistors due to an incomplete OFF-state of the transistors during an inactive state of the sense amplifier.
FIG. 20 shows the circuit configuration and current flow of the sense amplifier during an activate state thereof. Transistors FSAPT and FSAET are tuned ON, and VARY and VSSSA voltages are supplied to power source lines PCS and NCS, respectively. In the example of FIG. 20, bit lines BL and /BL assume H-level and L-level, respectively, whereas p-channel transistor P201 and n-channel transistor N202 are ON, and p-channel transistor P202 and n-channel transistor N201 are OFF in the sense amplifier. In this state, the leakage currents include a first leakage current which flows though a current path-1 from power source line PCS via p-channel transistor P202 and n-channel transistor N202, which are OFF, toward power source line NCS, and a second leakage current which flows through path-2 from power source line PCS via p-channel transistor P201 and n-channel transistor N201, which are OFF, toward power source line NCS. In short, the sense amplifier which is active during the active standby period increases the leakage current and thus increases the power dissipation in the conventional semiconductor memory device.
Patent Publication JP-2001-6364A describes a technique for reducing the leakage current or penetrating current in the sense amplifier, wherein the sense amplifier is divided into four blocks, which are provided with respective switches between the blocks and the power source line and between the blocks and the ground line. In one or some of the blocks having an output line now selected, a corresponding switch or switches are turned ON to supply the power source, whereas switches in the other blocks are turned OFF to thereby reduce the penetrating current in the sense amplifier.
The semiconductor memory device has a large number of sense amplifiers. In the semiconductor device described in the above publication, the sense amplifies are maintained in an active state during the active standby period. However, the leakage current of the sense amplifiers may cause the semiconductor memory device not to satisfy the IDD3 (active standby current or active power-down standby current) code specified for the active standby period of the memory device. In the above patent publication, the blocks not used are isolated off from the power source line to inactivate the sense amplifier. However, in a DRAM device, the data of the selected memory cell must be amplified and restored in the memory cell after the readout of data from the memory cell, and thus the sense amplifiers must not be inactivated without consideration of this fact. The above patent publication is silent to this fact, and thus the invention of this publication cannot be expected to solve the above problem in the DRAM device.